Dynamically partitionable digital video encoder processor
US5644504A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Mar 27, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/172
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a digital video encoder processor for discrete cosine transform encoding. The discrete cosine transform encoding includes the encoding steps of (1) determining the discrete cosine transform field or frame type, (2) addressing individual pixels as either (i) vertically adjacent pixels on consecutive Odd and Even field lines, or (ii) vertically adjacent pixels on consecutive Odd field lines, then consecutive Even field lines; or (iii) vertically adjacent pixels on consecutive Even field lines, then consecutive Odd field lines. These subtractions may be performed between (i) consecutive lines, (ii) odd lines, or (iii) even lines. The next step is finding the smallest variance of the above subtractions to determine the discrete cosine transform coding type. The subtractions are carried out in a dynamically partitionable processor having a plurality of datapaths. The datapaths are partitionable by the action of running opcode into (i) a single wide datapath, and (ii) a plurality of narrow datapaths for calculating the absolute value of the difference between two pixels, and accumulating the results of the subtraction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.