Non-volatile memory having a cell applying to multi-bit data by multi-layered floating gate architecture and programming method for the same
US5644528A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 21, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Nov 21, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5612
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An object of the present invention is to contribute to increase of storage capacity of a memory. A nonvolatile memory having a cell applying to multi-bit data by multi-layered floating gate architecture. The memory has a storage cell transistor which comprises a semiconductor substrate 1, source 2, drain 3 and control gate 5. The storage cell transistor, furthermore comprises a plurality of floating gates 4B.sub.1 -4B.sub.n which are arranged in order between a channel and the control gate. Two or more bits data can be saved per one storage cell. According to this architecture, an integration factor per one storage cell leaps upward since a necessary number of floating gates are stacked to overlie each other, the particular number corresponding to the number of bits to be stored therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.