Apparatus for accessing an extended data output dynamic random access memory
US5644549A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 21, 1996 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Mar 21, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for accessing an extended data output dynamic random access memory (EDO DRAM) is disclosed. A conventional fast page mode (FPM) DRAM is converted by the present invention to conform to an EDO DRAM. The present invention comprises a conventional FPM DRAM, a read-cycle generating circuit for generating a signal that defines a read cycle, a flip-flop for latching data signals from the FPM DRAM, an output control circuit for generating a control signal to control a data switch that will pass the latched data signals. The data signals come directly from the FPM DRAM and the latched data signals come from the data switch are combined to form extended data signals coupled to a system data bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.