Method and apparatus for converting logic test vectors to memory test patterns
US5644581A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 26, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Jun 26, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318342
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Logic test vectors, used for testing logic circuitry on a logic tester, are converted to test patterns having a format that is used by a memory tester. This allows an integrated circuit having both logic circuitry and a memory array to be tested on a memory tester. A software tool, or computer program, is used to convert the logic test vectors to test patterns, and also generates the memory test code for applying the test patterns to, for example, a logic intensive integrated circuit memory. The software tool is encoded using a high-level programming language and is executed on a computer system (60). The program allows the logic intensive integrated circuit memory to be tested on a memory tester, as compared to testing the integrated circuit memory on a logic tester, significantly reducing testing costs associated with manufacturing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.