Digital phase selector system and method
US5644604A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 1994 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Nov 14, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0045
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and method for transferring data between clock domains operating at substantially the same frequency continuously compares the relationship between a delayed data phase signal driven by a non-delayed source domain clock and a data phase signal sampled by a delayed receiving domain clock. The result of the comparison determines along which one of multiple data paths within the synchronizing circuit the transfer of the data frame will take place. Several data paths with different delays (at least two) transfer the data frame and clock signals. An XNOR comparator responds to the relationship between a delayed data phase signal driven by a non-delayed source domain clock and a data phase signal sampled by a delayed receiving domain clock to determine which one of the multiple data paths transfers the data frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.