Receiver with two synchronization loops
US5644606A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Aug 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/3827
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Digital transmission system (10) for digitally modulated signals, comprising a receiving device (14) which includes a demodulator (110), processing apparatus (120) and carrier synchronizing apparatus (16) for estimating and compensating for synchronization errors. The synchronizing apparatus includes a first loop (1) for phase/frequency correction and a second loop (2) for phase correction, the operation of these loops being controlled by a mode detector (130) depending on whether the receiving device is seeking to unlock or lock. The second loop (2) transforms a phase error signal into a phase correction signal which is mixed in mixer (246) with the signal coming from the demodulator. Preferably, the signals are modulated via a coded modulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.