Hybrid analog-digital phase error detector
US5644743A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1995 |
| Grant date | Jul 1, 1997 |
| Priority date | — |
| Expiry date | Dec 4, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D13/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A hybrid analog-digital phase error detector (107) is utilized for detecting a phase error between first and second clock signals (132, 104). Digital and analog phase error detectors (108, 116) are connected to the first and second clock signals (132, 104), and are utilized for producing digital and analog phase error values (110, 118). The digital and analog controllers (112, 120) connected to the digital and analog phase error detectors (108, 116) execute digital and analog control algorithms based on the digital and analog phase error values (110, 118) to produce digital and analog control signals (114, 122). A summer (124) connected to the outputs of the digital and analog controllers (112, 120) combines the analog control signal (122) and the digital control signal (114) to produce a composite control signal (126) representing the phase error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.