Method of bonding wafers having vias including conductive material
US5646067A · kind A · utility
312Cited by
46References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 5, 1995 |
| Grant date | Jul 8, 1997 |
| Priority date | — |
| Expiry date | Jun 5, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A surface mountable integrated circuit and a method of manufacture are disclosed. A wafer 110 has a die with an integrated circuit 119 in one surface of the wafer. A via 130 extends to the opposite surface. The via has a sidewall oxide 131 and is filled with a conductive material such as metal or doped polysilicon. The metal may comprise a barrier layer and an adhesion layer. The second end of the via can be fashioned as a prong 233 or a receptacle 430. Dies with vias can be stacked on top of each other or surface mounted to printed circuit boards or other substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.