Method for fabricating CMOS field effect transistors having sub-quarter micrometer channel lengths with improved short channel effect characteristics

US5646435A · kind A · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Charles C. Hsu · Baoshan, TW
• Mong-Song Liang · Baoshan, TW

Key dates

• Filing date: Apr 4, 1995
• Grant date: Jul 8, 1997
• Expiry date: Apr 4, 2015

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/038

Abstract

A reverse self-aligned field effect transistor having sub-quarter micrometer (<0.25 um) channel lengths and shallow source/drain junction depths was achieved. The method for fabricating the FET includes a conducting layer that is deposited and patterned over the source/drain areas of the FET. The sub-quarter micrometer channel length was achieved by reducing the channel opening formed in the conducting layer using sidewall spacer techniques. The conducting layer on the substrate and under the source/drain polysilicon layer also serves as an interface to the diffusing source/drain dopants, and shallow junctions are formed that are about 0.06 to 0.08 um depth. The conducting layer also serves as a low resistant ohmic contact to the source/drain areas.