Digital phase detector employing a digitally controllable delay line
US5646519A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Jul 8, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase detector composed of: a digitally controllable signal delay device having a signal input, a signal output and a control input, the delay device being operative for conducting a signal from the signal input to the signal output with a time delay having a duration determined by a control signal supplied to the control input, the signal input being connected to receive either an input signal or a digital local clock signal; a phase relation detector connected to receive a first input signal from the signal output of the signal delay device and a second input signal constituted by the one of the input signal and the digital local clock signal which is not received by the signal input of the signal delay device, for periodically comparing the phases of the first and second input signals and for producing a binary output signal composed of a succession of signal segments, each segment having a first value when the first input signal is leading the second input signal in phase and a second value when the first input signal is lagging the second input signal in phase; and a digital modulator connected for receiving the binary output signal from the phase relation detector a…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.