High voltage tolerant CMOS input/output pad circuits
US5646809A · kind A · utility
28Cited by
5References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 1995 |
| Grant date | Jul 8, 1997 |
| Priority date | — |
| Expiry date | Aug 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high voltage tolerant CMOS output driver circuit and high voltage tolerant CMOS input receiver circuit, through the use of shield transistors and the redefinition of the substrate of the PFET devices, is provided. The invention may be incorporated for protection in integrated circuits operating with a lower power supply voltage than externally interfaced devices operating with a higher power supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.