Multiple block transfer mechanism
US5647057A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 1994 |
| Grant date | Jul 8, 1997 |
| Priority date | — |
| Expiry date | Sep 9, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A block data transfer system may comprise a microprocessor integrated within a bus controller, a bus, and a plurality of computer boards coupled together via the bus. A (programmable array logic device), integrated within the bus controller, allows an efficient block transfer of data between components on the computer boards by asserting a binary signal to indicate to the bus controller when to continue the data transfer and when to truncate the data transfer. The utilizes a counter, dependent upon the data transfer size, to control the binary indication signal. The binary signal overrides the architectural data transfer protocol, thereby eliminating "protocol overhead" timing associated in multiple data transfers by allowing the entire data block to transfer within one transfer protocol period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.