Autodoping prevention and oxide layer formation apparatus
US5648282A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 1993 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | May 24, 2013 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/92
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
To form a MOS transistor with a LDD structure, the transistor is formed in a well region. There is formed a gate oxide layer on a silicon substrate and an N.sup.+ type poly-silicon layer serving as a gate electrode is formed on the gate oxide layer. The poly-silicon layer is doped with phosphorus atoms. Then, a surface of the silicon substrate is exposed in a LDD region serving as a source/drain region as formed with phosphorus implantation. The LDD region of the transistor is implanted with phosphorus ions. Subsequently, a side wall is formed on the gate electrode. To enhance the adherence of the side wall material and activate the phosphorus ions implanted in the previous step, annealing and formation of an oxide film are effected. This thermal treatment prevents the phosphorus atoms from deporting the gate electrode of the poly-silicon layer and self diffusing into the LDD region. This thermal treatment is performed with nitrogen gas containing 1 to 5 volume % at the initial stage thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.