Trench MOS-gated device with a minimum number of masks
US5648670A · kind A · utility
115Cited by
14References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 7, 1995 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Jun 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A low-voltage high-current discrete insulated-gate field-effect transistor which is made by a very economical process with two silicon etches. A buried poly gate gates conduction along a trench sidewall. The channel is provided by the residuum of an epi layer, and the source diffusion is provided by an unmasked implant which is screened only by various grown oxides.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.