Static timing verification in the presence of logically false paths
US5648909A · kind A · utility
25Cited by
17References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1995 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Jun 12, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method for improving a circuit having a logically false path through static analysis of a software model, a computer receives information describing the false path, determines a true path alternate to the false path, and analyses the circuit model with respect to the true path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.