Method of minimizing area for fanout chains in high-speed networks
US5648911A · kind A · utility
21Cited by
6References
5Claims
0Family size
Inventors
Key dates
| Filing date | Aug 30, 1996 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Aug 30, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method for efficiently providing an optimized fanout network includes the steps of providing a series chain of inverters for driving a number of loads. Each load is assigned to a given location of the inverter chain according to the polarity and the required time of the load. Tree-covering techniques are used in conjunction with dynamic programming to minimize the total area of the fanout chain by selecting and sizing the gates to be used in the fanout chain. With such an arrangement, a minimal area fanout chain which satisfies the timing constraints of each load is provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.