System and method for recording sufficient data from parallel execution stages in a central processing unit for complete fault recovery
US5649088A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1996 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Aug 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault recovery system and method that deterministically reconstructs the instruction stream of a multiple execution stage ("pipelined") processor. A log ("queue") is provided for each critical data item to record the instructions, operations and effects as processing proceeds. Also, rather than merely freezing the execution of a specific stage upon occurrence of a fault, all stages are stopped so that each stage does not overwrite log information that is needed to reconstruct the instruction flow immediately preceding the invocation of any fault recovery operation. The fault recovery operation may then serially reconstruct the instruction flow, advantageously starting with the instruction where the fault occurred, working to reconstruct from that instruction to the last instruction that was executing before the fault recovery operation began.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.