Fault tolerant multiprocessor computer system
US5649090A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 1991 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | May 31, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2268
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant computer system includes at least two central processing units each having a cache memory and a parity error detector adapted to sense parity errors in blocks of information read from and write to cache and to issue a cache parity read or write error flag if a parity error is sensed. A system bus couples the CPU to a System Control Unit having a parity error correction facility, and a memory bus couples the SCU to a main memory. An error recovery control feature distributed across the CPU, including a Service Processor and the operating system software, is responsive to the sensing of a read parity error flag in a sending CPU and a write parity error flag in a receiving CPU in conjunction with a siphon operation for transferring the faulting block from the sending CPU to main memory via the SCU (in which given faulting block is corrected) and for subsequently transferring the corrected memory block from main memory to the receiving CPU when a retry is instituted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.