Method and apparatus for address extension across a multiplexed communication bus
US5649125A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1995 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Oct 30, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system (10) having a bus controller (5) and a multiplexed communication bus (22) and provides a portion of the valid address information during the data phase. In one embodiment, in response to an address extension control signal, the bus controller (5) allocates the communication bus (22) to provide the address extension on conductors not needed for data, reducing the need for address latch circuitry. In an alternate embodiment, the bus controller (5) provides burst transfers where the processor core (2) increments a portion of each address with each data in the burst. For such burst transfers, the length of the desired data is controlled by a sizing signal (42) from the core (2) or from cache and the increment size is supplied by the system resource (7).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.