Apparatus, systems and methods for improving data cache hit rates
US5649144A · kind A · utility
39Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 29, 1996 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Aug 29, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/6026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing system is provided which generates a memory address and presents the memory address to a cache to retrieve corresponding data when such corresponding data is encached therein. The memory address is presented to a main memory to retrieve the corresponding data therefrom when such corresponding data is not encached in cache. An offset address to the memory address is used to obtain a prefetch address which in turn is presented to the main memory to retrieve selected information stored within memory. The cache then stores the selected information retrieved from the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.