Scannable last-in-first-out register stack
US5649150A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 12, 1995 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Apr 12, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/003
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A scannable LIFO register stack in which registers are arranged in a stack with each register having a number of bit locations. Each register is in communication with an adjacent register located above and below it. In particular, each bit location in a register within the stack located between the top and the bottom register is in communication with a corresponding bit location in an adjacent register located above the register and a corresponding bit location in an adjacent register located below the register. Except for the last bit, each bit location in the top register has a connection to an offset bit location in the bottom register. Shifting a bit of data from a bit location in the top register to the offset bit location in the bottom register results in the bit being shifted to the right by one bit location according to the present invention. The last bit location in the top register has an output that is used as a scan output. The first bit location in the bottom register has an input used as a scan input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.