Method and apparatus for acquiring bus transaction address and command information with no more than zero-hold-time and with fast device acknowledgement
US5649175A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 1995 |
| Grant date | Jul 15, 1997 |
| Priority date | — |
| Expiry date | Aug 10, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for acquiring address and command information related to a synchronous bus transaction with at most zero hold-time over substantially the duration of the bus transaction. Due to state changes, bus transaction address and command information may become invalid over the duration of the bus transaction. A transparent latch circuit is used to make the information available as soon as the information is received and to acquire valid information related to the bus transaction before a rising clock edge of the next clock cycle following a bus transaction request. A synchronous flip-flop circuit is utilized simultaneously to capture alternate valid information related to a bus transaction having at most zero hold-time. The acquired valid information and the alternately acquired valid information ensure that stable and valid bus transaction information are available over substantially the duration of the transaction. Moreover, by decoding the information as soon as they are received (i.e., before the transparent latch circuit closes), a fast bus transaction acknowledgement signal can be generated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.