Method of manufacturing thin film transistor
US5650339A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 1995 |
| Grant date | Jul 22, 1997 |
| Priority date | — |
| Expiry date | Dec 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes an underlying layer formed by a first insulation layer, a plurality of island semiconductor layers formed on the first insulation layer, source and drain regions formed in each of the island semiconductor layers, a first gate electrode formed between the source and drain regions and formed on and insulated from the island semiconductor layer, a second insulation layer formed on the sides of the island semiconductor layer and along the periphery of the first gate electrode, the second insulation layer being higher than the surface of the island semiconductor layer and lower than the surface of the first gate electrode, and a second gate electrode formed over both the first gate electrode and the second insulation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.