Circuit technique for implementing programmable zeros in high speed CMOS filters
US5650747A · kind A · utility
7Cited by
7References
17Claims
0Family size
Inventor
Key dates
| Filing date | Oct 5, 1995 |
| Grant date | Jul 22, 1997 |
| Priority date | — |
| Expiry date | Oct 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H11/0433
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit technique for implementing programmable zeros in high speed CMOS filters is disclosed. The circuit uses both PMOS and NMOS type transconductance elements to implement a biquad with a real zero and two complex poles. The NMOS transconductance element is biased by the total bias current required by several PMOS transconductance elements and can thus provide larger transconductance as required by the equalization function. Programmability is achieved by dividing the NMOS transconductance elements into a plurality of identical sub-elements that are connected in parallel via digitally programmable switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.