Internetworking device with enhanced packet header translation and memory
US5651002A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 12, 1995 |
| Grant date | Jul 22, 1997 |
| Priority date | — |
| Expiry date | Jul 12, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/18
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An internetworking device providing enhanced packet header translation for translating the format of a header associated with a source network into a header format associated with a destination network of a different type than the source network. The device includes a memory for storing an address portion of a received packet header in a first block of buffer locations and the remainder of the received packet in a second block of buffer locations, spaced from the first block of buffer locations by a gap. The gap permits supplemental header information to be written into the buffer when necessary for translation. The device further includes a split memory, having an SRAM portion and a DRAM portion allocated to each buffer, with at least the address portion of a received packet and the gap located in the SRAM portion, so as to optimize the translation performance of the device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.