Apparatus for reducing jitter of a spectrum spread clock signal and method therefor
US5651035A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1995 |
| Grant date | Jul 22, 1997 |
| Priority date | — |
| Expiry date | Apr 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An accumulator stores a signal representation of an accumulated angle that is incremented by an input angle in response to a reference clock pulse. The most significant bit (MSB) of the accumulated angle signals drives the input of a phase locked loop of the type that includes a loop filter, a frequency divider and a voltage controlled oscillator (VCO). A charge is injected into the loop filter during an overshoot interval during which the output of the frequency divider differs from the MSB. A compensating charge is injected into the loop filter to compensate for the charge injected during the overshoot interval. Jitter free spectrum spread clock pulses are provided by the VCO in response to the MSB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.