Pipelined data processor that detects an illegal instruction by detecting legal instruction operation codes
US5651122A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 13, 1991 |
| Grant date | Jul 22, 1997 |
| Priority date | — |
| Expiry date | May 13, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30145
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipelined data processor (10) has a control unit (14') that detects an illegal instruction as well as legal instruction opcodes. An opcode decoder (28) decodes instructions. In response to decoding an illegal instruction, opcode decoder (28) provides no output signal. In response to decoding a legal instruction, opcode decoder (28) provides one of a plurality of output signals. A ROM (27) provides a first output in response to receiving no output from the decoder (28), and provides one of a plurality of second outputs in response to receiving one of a plurality of output signals from decoder (28). The first output of the ROM (27) is a first microword of a routine for processing the illegal instruction. Each of the second outputs of the ROM (27) is a first microword of a routine for processing the legal instruction received from the decoder (28).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.