Method and apparatus for reducing transitions on computer signal lines
US5651126A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1992 |
| Grant date | Jul 22, 1997 |
| Priority date | — |
| Expiry date | Jun 26, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/161
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for eliminating unnecessary address transitions on an DRAM address bus and DRAM write enable line. In a known DRAM controller and DRAM array, all address transitions on the CPU address bus are mirrored by address transitions on the DRAM address bus. The present invention eliminates all address transitions not associated with an actual DRAM access cycle by eliminating the DRAM controller's address multiplexer and replacing it with a multiplexing driver circuit and a bus holder circuit. In a similar fashion, a DRAM write enable circuit eliminates all transitions on the DRAM write enable line that are not associated with actual DRAM access cycles. Although specifically discussed in terms of a DRAM array and its associated circuitry, the portion of the present invention that reduces address transitions on the DRAM address lines could be used in any device currently using a multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.