Data processor with controlled burst memory accesses and method therefor
US5651138A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 1994 |
| Grant date | Jul 22, 1997 |
| Priority date | — |
| Expiry date | Dec 21, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4243
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor (21) includes an external bus interface circuit (33) responsive to two internal bus master devices (30, 34) to perform either a fixed or a variable burst access. The data processor (21) activates an external control signal to indicate whether a burst access is a fixed or a variable burst access. The data processor (21) indicates the port size of the accessed memory region by providing a port size signal to the external bus interface circuit (33). The external bus interface circuit (33) is responsive to the port size signal to break up the burst cycle into two or more burst cycles on the external bus (22, 23), if the accessed location corresponds to a memory (24) with a different port size than the internal bus (31).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.