Structuring of printed circuit boards
US5651899A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1995 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Sep 29, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/1142
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In the method according to the invention for the production of multilayer foil printed circuit board from preliminary products (A), with current paths (B) structured in electrical conductive layers (1,3) and with electrically conductive metal platings (C,D) from conductive layer (1) to conductive layer (3) through an insulating layer (2), or for producing semifinished products for such foil circuit boards, in first method steps a structuring means (7,7',13) is applied in controlled, local manner to the preliminary product (A) and resist layers (8,9) are coated with the preliminary product (A), the structuring means (7,7',13) being applied either to the resist layers (8,9) and the resist layer (8,9) is locally removed, or the resist layers (8,9) are applied to the structuring means (7,7',13) and in a further method step the applied structuring means (7,7',13) are removed, so that openings (10,10') are formed in the resist layers (8,9) and extend down to the insulating layer (2) and in a further method step through or blind holes (11,11') are locally etched in the insulating layer (2) at the position of the openings (10,10') and for producing electrically conductive metal platings (C…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.