Error rate measuring apparatus
US5652760A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Nov 7, 1995 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Nov 7, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/16
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An error rate measuring apparatus includes a demodulator, and data from the demodulator is applied to a decoding circuit in which an error bit number is evaluated for each of a BIC portion and a packet portion. In the BIC portion, if a synchronization is settled, the error bit number is evaluated by comparing received BICs and a predetermined BIC pattern, and if the synchronization is not settled, the error bit number is determined as eight (8) bits. In the packet portion, if a frame synchronization is settled and decoding is successful, the error bit number is calculated by comparing data before decoding and data after decoding with each other. If the frame synchronization is settled but the decoding is unsuccessful, a presumed error bit number is set according to the number of packets being decoded successfully in a first time horizontal direction, and if the frame synchronization is not settled, a predetermined error bit number is set. In each of the BIC portion and the packet portion, a bit error rate is calculated on the basis of the error bit number for each measurement range, and displayed on a monitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.