Method and apparatus for decreasing the cycle times of a data processing system
US5652774A · kind A · utility
6Cited by
11References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 8, 1996 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Jul 8, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/384
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing the number of cycles required to implement load instructions in a data processing system having a Central Processing Unit (CPU). The CPU includes a rename register file that can be used in whole or in part for retaining cache lines from previously executed load instructions. The rename register file is then used by subsequent instructions (e.g. load instructions) requiring the data previously loaded therein. Thus, reducing the cycles normally associated with retrieving the data from the cache for the subsequent instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.