Bus deadlock prevention circuit for use with second level cache controller
US5652846A · kind A · utility
4Cited by
6References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 3, 1995 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Jul 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system which corrects errors in a second level cache controller. The cache controller erroneously provides the cycle lock signal for the entire period of a writeback cycle followed by an I/O bus access, thus causing a deadlock if an I/O bus master needs access to the host bus at the same time. A circuit determines when the writeback cycle is occurring and masks the lock signal during the writeback operation, so that the long lock assertion is not present and the arbiters can properly control the access to the buses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.