Low latency cadence selectable interface for data transfers between busses of differing frequencies
US5652848A · kind A · utility
26Cited by
23References
7Claims
0Family size
Assignee
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Key dates
| Filing date | May 24, 1996 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | May 24, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interface with resources to selectively optimize burst mode data transfers from one bus to another through an automated selection and generation of a cadence. In one form, the cadence is selected based upon memory access latency characteristics, the relative widths of the busses, and the relative clock frequencies of the busses. The selected cadence is provided as a pacing ready signal to the bus receiving the transferred data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.