DSP co-processor for use on an integrated circuit that performs multiple communication tasks
US5652903A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1994 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Nov 1, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/38
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A DSP co-processor (72) that is used on an integrated circuit (24) that provides multiple communication functions is accomplished by providing a data bus interface (320), a sequencer (328), internal memory (33), and a data core (322). The sequencer (328) stores in a hardware format a signal processing algorithm (332) and, upon receipt of an operational command, provides address control signals (334) and operation control signals (336) to the data core (322). The data core (322), which includes an address generation unit (340) and an arithmetic unit (344), executes, via the arithmetic unit, operational instructions of the signal processing algorithm to produce resultant signals from the input samples, the intermediate resultants, and the algorithm co-efficients.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.