High speed mask and logical combination operations for parallel processor units
US5652907A · kind A · utility
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6References
10Claims
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Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Jul 29, 1997 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a plurality of parallel processor units with each processor unit having an output bus of n bits and an associated mask register is provided. The computer system comprises a bus unit, coupled to the output bus of each processor unit and each associated mask register, for masking the output bus bits with bits in the mask register of each processor unit and logically combining the resulting masked bits from each processor unit into an output bus of n bits in one computer operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.