Semiconductor device
US5654571A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 1994 |
| Grant date | Aug 5, 1997 |
| Priority date | — |
| Expiry date | Oct 19, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A semiconductor device, such as a MOS integrated circuit, provides an internal circuit whose primary stage is configured by an inverter circuit consisting of p-channel and n-channel MOS transistors. The sources of the MOS transistors are connected with a first pair of power-supply terminals respectively, while the gates of the MOS transistors are connected together to form a common gate terminal to which a voltage input applied to an input is terminal. The MOS integrated circuit provides first and second input protection circuits which are connected together between the input terminal and common gate terminal. The first input protection circuit is connected with a second pair of power-supply terminals which is provided independently of the first pair of power-supply terminals. When an abnormal voltage input is applied to the input terminal, the first input protection circuit is activated to perform a voltage clamping by releasing an electric current. If the abnormal voltage input is a sharp surge-pulse input, the second input protection circuit is activated as well so that a potential variation at the common gate terminal, which is caused by the abnormal voltage input, is followed …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.