Circuit wafer and TEG test pad electrode
US5654582A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1995 |
| Grant date | Aug 5, 1997 |
| Priority date | — |
| Expiry date | May 5, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor wafer and semiconductor device manufactured from the wafer. The wafer has a conductive layer 33A intermittently formed in the longitudinal direction of a scribe area 2. The conductive layer's width shorter width than its length and shaped so that the scribe area is cut in the longtitudinal direction including the location of said width. The invention provides a semiconductor wafer not giving rise to faults, such as short-circuiting due to shavings, and not requiring any modification in the scribed width, blade width, or pad size when sawing conductive layers in the scribe area, such as the above-mentioned pads of the TEG.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.