Scan circuit having a reduced clock signal delay
US5654659A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1995 |
| Grant date | Aug 5, 1997 |
| Priority date | — |
| Expiry date | Feb 28, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/133
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A scan circuit includes a plurality of stages of cascaded pulse delay transfer circuits each including a single-phase-clock controlled inverter connected in cascade and configured to receive a given pulse signal from a preceding stage so as to transfer the received pulse signal to a next stage at a delayed timing in synchronism with a clock signal, and a two-input logic gate having a first input connected to an output of the associated single-phase-clock controlled inverter and a second input receiving the same clock signal. The two-input logic gate of an odd-numbered stage includes a NOR gate, which has an output connected to a non-inverting output buffer. The two-input logic gate of an even-numbered stage includes a NAND gate, which has an output connected to an inverting output buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.