Externally controlled DSP with input/output FIFOs operating asynchronously and independently of a system environment
US5655090A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Aug 5, 1997 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2027/0051
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A means of making a digital signal processing function perform independently of the system processor and appear as a hardware FIFO. The architecture of the present invention comprises a digital signal processing means connected between the data output of a first FIFO buffer and the data input of a second FIFO buffer, a control means for controlling the digital signal processing means as a function of the presence and absence of data in the first FIFO buffer and said second FIFO buffer and control signals received from a source of control signals. Data throughput is performed asynchronously and independently of the system environment and comprises the following steps: receiving data on the data input of the first FIFO buffer, transferring that data to the digital signal processor, processing the data, then transferring the processed data to the second FIFO buffer to be output when the data receiver is ready to accept to data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.