DMA controller having a plurality of DMA channels each having multiple register sets storing different information controlling respective data transfer
US5655151A · kind A · utility
61Cited by
40References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1994 |
| Grant date | Aug 5, 1997 |
| Priority date | — |
| Expiry date | Jan 28, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A direct memory access (DMA) controller is connected with the CPU bus of a computer system through a bus interface and also to an I/O bus, which is connectable to one or more I/O controllers. The DMA controller contains multiple channels, each corresponding to a particular I/O controller, which are coupled to both the bus interface and the I/O bus. Each of the channels contains at least one register set storing information for the transfer and a data buffer holding the data during a transfer between the I/O bus and the CPU bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.