Circuit arrangement for generating a bias potential
US5656927A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1996 |
| Grant date | Aug 12, 1997 |
| Priority date | — |
| Expiry date | Sep 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/205
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
Circuit arrangement for generating a bias potential includes a first transistor connected on a collector side thereof to a supply potential, a first resistor connected between a base and the collector of the first transistor, a first current source connected between the base of the first transistor and a reference potential, a second current source connected between an emitter of the first transistor and the reference potential, a second transistor connected on a collector side thereof to the supply potential and on a base side thereof to the emitter of the first transistor, a third current source connected between the emitter of the second transistor and the reference potential, a third transistor carrying the bias potential on a collector side thereof, a second resistor connected between the emitter of the second transistor and a base of the third transistor, a third resistor connected between the collector of the third transistor and the supply potential, a first diode connected in the forward direction thereof between the base of the third transistor and the reference potential, and a fourth resistor connected between an emitter of the third transistor and the reference potenti…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.