Clock synthesizer dual function pin system and method therefor
US5656959A · kind A · utility
24Cited by
12References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 24, 1995 |
| Grant date | Aug 12, 1997 |
| Priority date | — |
| Expiry date | Nov 24, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved clock synthesizer system and method therefor is described which uses a plurality of dual function pins to apply a frequency selection code while in a first operating mode and to transmit buffered clock signal while in a second operating mode to accomplish required system functions with a reduced overall pin count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.