Timing verification using synchronizers and timing constraints
US5657239A · kind A · utility
39Cited by
6References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1992 |
| Grant date | Aug 12, 1997 |
| Priority date | — |
| Expiry date | Oct 30, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-based method and program for improving a design of a circuit through analysis of a computer stored model of the circuit. Individual synchronization points are identified in the circuit at each of which a signal may be blocked or allowed to pass in response to appearance of a second signal at the synchronization point. The timing of the circuit is verified based on the individual synchronization points.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.