System for protecting memory accesses by comparing the upper and lower bounds addresses and attribute bits identifying unauthorized combinations of type of operation and mode of access
US5657475A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1996 |
| Grant date | Aug 12, 1997 |
| Priority date | — |
| Expiry date | Jan 4, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected. As the structure of the protection mechanism does not require separate cycles in the processor, and simply monitors the memory bus for memory accesses, memory protection and detection can be performed with no additional overhead at the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.