Method and apparatus for batchable frame switch and synchronization operations
US5657478A · kind A · utility
63Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 16, 1996 |
| Grant date | Aug 12, 1997 |
| Priority date | — |
| Expiry date | May 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/121
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A system and method that avoids performance bottlenecks at the host processor while avoiding tearing of the displayed image. In one embodiment, the system is composed of the host processor, a first in first out (FIFO) buffer, a co-processor, multiple frame buffers, a display controller and a display. The host and the co-processor are configured to enable the host to selectively batch graphic commands to the co-processor. The small set of commands provides the flexibility to selectively batch commands and selectively synchronize the host processor to the co-processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.