Circuit and method for correcting phase error in a multiplier circuit
US5659263A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1996 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Mar 25, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D13/008
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit and method for reducing a phase error at the output terminal (48) of a multiplier circuit (41) is provided. The phase error arises when first and second input signals having asymmetric signal paths are multiplied in the multiplier circuit (41). A second multiplier circuit (42) multiplies the in-phase and quadrature signals and produces an output signal at an output terminal (49) which contains the phase error but with the opposite polarity as the phase error produced by the first multiplier circuit (41). The signals at the output terminals (48) and (49) are summed in a summing circuit (43) to produce a third output signal in which the phase error is canceled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.