Method and apparatus for verifying test information on a backplane test bus
US5659552A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 1995 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Oct 17, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Verification of test information transmitted across an 1149.1 backplane test bus between a circuit board (12.sub.1) and a test master (14) is accomplished by having both the test master and the circuit board compute a cheek code for each block of information that is transmitted by, or received at, the board. During intervals other than one of the active Boundary-Scan states, the test master (14) acquires the check codes produced at the circuit board (12.sub.1) and compares them to the corresponding codes generated by the tests master. Any difference between the corresponding codes generated by the test master and the circuit board signifies a transmission error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.