Programmably configurable host adapter integrated circuit including a RISC processor
US5659690A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 15, 1992 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Oct 15, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The host adapter integrated circuit is a one chip high performance bus master host adapter for (i) connecting a first bus having a specified protocol for transferring information over the first bus and a first data transfer speed to a second bus having a specified protocol for transferring information over the second bus and a second data transfer speed, and (ii) transferring information between the two buses. The host adapter integrated circuit, hereinafter host adapter, includes a novel reduced instruction set computing (RISC) processor, a first interface module circuit connectable to the first bus and coupled to the RISC processor, a second interface module circuit connectable to the second bus and coupled to the RISC processor, and a memory circuit means connected to the first interface module circuit and to the second interface module circuit and coupled to the RISC processor. An I/O bus interconnects the first interface module circuit, the second interface module circuit, the memory circuit means, and the RISC processor. The I/O bus supports a read and a write operation by the RISC processor in single clock cycle of the RISC processor. The host adapter supports many features …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.