Synchronous bus and bus interface device
US5659718A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 1994 |
| Grant date | Aug 19, 1997 |
| Priority date | — |
| Expiry date | Aug 19, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4022
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A high performance bus and bus interface device for interconnecting numerous devices without using dedicated high current drivers at each device. The bus is synchronous and divided into a plurality of primary local busses and at least one global bus. Data can be transferred from a first device over a first primary local bus through a first global transceiver, over the global bus to a second global transceiver, and then to a second device through a second primary local bus. The bus is driven to a known state at the end of each burst of data transmitted by a device, before the bus is relinquished to another device. Buffers are provided in each device on the primary local bus which can be accessed by other devices. Buffer management includes: (1) determination by each transmitting device of buffer availability at each receiving device; (2) "claiming" use by the transmitting device of a buffer in the receiving device for transfers from the transmitting device, including locking out other devices from writing to that buffer; (3) capability of the transmitting device to move received data to the buffer in the receiver; and (4) notification to all devices that the transfer is complete. Th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.